Abstract
This paper presents a current memory cell (CMC) which can be used as basic elements of current pipeline analog-to-digital converter stages. This CMC is based on a fully differential structure which uses the Miller effect to reduce charge-injection errors. Using a 0.35/spl mu/m 3.3V CMOS process, results show that the signal-dependent charge-injection error is less than 20nA for [-200/spl mu/A;200/spl mu/A] dynamic input current range. The acquisition time for a 200/spl mu/ input step transition to achieve a 14 bit settling accuracy is 22ns. The active chip area and the power consumption of the proposed CMC are about 0.042mm/sup 2/ and 6mW, respectively.
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