Settling accuracy and noise performances in switched current grounded gate class AB memory cells

Abstract

Nowadays, Switched Current Technique is at the aim of interest. However, the running of this kind of cells is disturbed by several error sources which affect its performances. The Grounded Gate Class AB Memory Cell is adopted because it solves some of non-idealities affecting the conventional Class A memory cell. Namely, the output to input conductances ratio error and charge injection error. Nevertheless, this cell has to be more improved. In this paper we deal with improving the performances of the grounded gate class AB memory cells in terms of settling accuracy and dynamic ranges. Mathematical models are built in order to optimize the running of the treated cell. Optimum criteria for design parameters is derived for both settling characteristic and noise. A relation between settling accuracy and SNR is defined and is analytically shown to be dependent on the effective geometric dimensions of the memory transistor. MAPLE and AMS-0.35/spl mu/m process SPICE simulation results are presented and validate these analysis.