A new current mirror memory cell to improve the power efficiency of CMOS current mode analog circuits

Abstract

This work presents a new technique to improve the power efficiency of CMOS current mode analog circuits. Instead of using the first generation (FG) current memory cells as the major building block for CMOS current mode analog circuit design, we propose a new current mirror memory cell (CMMC). We present our argument by detailed analysis and simulation results to back up our claims. Two delay cells are designed using the FG current memory cell and CMMC. Simulation results show that our approach saves 38.46% of power while achieving similar performance compared with the first generation current memory cells.