Abstract
Field-programmable gate arrays (FPGAs) are pervasive in embedded systems requiring low-power utilization. A novel power optimization methodology for reducing the dynamic power consumed by the routing of FPGA circuits by modifying the constraints applied to existing commercial tool sets is presented. The power optimization techniques influence commercial FPGA Place and Route (PAR) tools by translating power goals into standard throughput and placement-based constraints. The Low-Power Intelligent Tool Environment (LITE) is presented, which was developed to support the experimentation of power models and power optimization algorithms. The generated constraints seek to implement one of four power optimization approaches: slack minimization, clock tree paring, N-terminal net colocation, and area minimization. In an experimental study, we optimize dynamic power of circuitsmapped into 0.12 µm Xilinx Virtex-II FPGAs. Results show that several optimization algorithms can be combined on a single design, and power is reduced by up to 19.4%, with an average power savings of 10.2%.
Highlights
Field-programmable gate arrays (FPGAs) handle most digital signal processing functions in an embedded platform
We seek to validate that the results we have seen in the previous sections utilizing XPower and our Low-Power Intelligent Tool Environment (LITE) tools are realizable in the real world
We present a variety of techniques that seek to reduce power by feeding power driven constraints into commercial off-the-shelf (COTS)
Summary
Field-programmable gate arrays (FPGAs) handle most digital signal processing functions in an embedded platform. Many embedded platforms, such as handheld devices, distributed sensors, and satellites, demand low power in order to increase their functional lifetime. While SRAM-based FPGAs have a short design cycle, steadily decreasing cost, and growing performance, power consumption remains a concern [1]. Power must be considered at every level, from VLSI issues such as transistor layout and leakage current, to the software that determines how efficiently a user’s design is implemented on an FPGA. There have been many FPGA power reduction approaches addressing different design levels. It has been shown that power can be addressed in the suite of computer-aided design (CAD) algorithms that place and route an end user’s circuit onto the FPGA fabric [7]
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