FPGA based DPWM/DPFM architecture for digitally controlled dc-dc converters

Abstract

This paper deals with design of Digital Pulse Width Modulator (DPWM) and Digital Pulse Frequency Modulator (DPWM) architectures with block RAM available in FPGA. Variable duty cycle pulse and variable frequency pulse are generated to control the switch of power converters. The proposed dual mode DPWM/DPFM architecture can control the switch of power converter under light and heavy load conditions. Clock divider is designed with 4 bit modulo 16 counter to deliver the desired clock to the various blocks in the architecture. Architecture is designed with Verilog hardware language, synthesized and implemented with Xilinx PlanAhead 14.2 tool for various bit sizes of duty cycle d(n) and frequency control inputs f(n). Proposed architecture can have a maximum operating frequency of 306 MHz and achieves higher resolution without using counter and delay line scheme utilized in traditional DPWM/DPFM architectures.