FPGA Implementation of High Speed Digital Pulse Width Modulator (DPWM) Technique for DC-DC Converter

K.K Varsha,P R Savitha

doi:10.17485/ijst/2019/v12i29/146969

Abstract

Objectives: Digital Pulse Width Modulator (DPWM) remains essential element in power controlling devices that command power switch of power converters. The focus of this study is to structure DPWM of FPGA base for DC chopper. Methods: Buck, Boost, Buck and Boost convertor versions are developed in MATLAB-SIMULINK. Verilog coding is performed for Digital Controller to operate for greater rates, which may be incorporated in high speed surroundings; synthesis is completed utilizing Xilinx ISE, along with Behavioral and Period simulation performed with Xilinx Simulator. After affirmation of code it is downloaded on FPGA Spartan 3AN board. The output is confirmed by means of Oscilloscope. Findings/Application: The resulting DPWM is a high speed and less power consuming architecture for Buck, Boost, Buck and Boost DC-DC converter. The utilization of Gray counter and One-hot encoder in DPWM has helped in speed improvement and reduced power consumption. The grey encoding method has fewer states in comparison with the sequential encoding method, which makes them quicker. The output is a Pulse-Width Modulation (PWM) signal, for varying clock frequency and duty cycle. The power consumed by DPWM for various frequencies was verified in comparison with the high frequency DPWM. For 6 MHz frequency, the power consumed by DPWM is 0.01486 w and that by a high frequency DPWM is 0.01486 w. The proposed DPWM can operate at a maximum frequency of 140.298 MHz. This DPWM is best suited for Buck, Boost, and Buck and Boost DC-DC converters. Keywords: DC–DC Converter, Field Programmable Gate Arrays (FPGA), Pulse-Width Modulation (PWM), Spartan, MATLAB, SIMULINK

Highlights

Current research tasks focused on boosting stable state along with the dynamic behaviour of DC-DC converters for high-performance, by signaling different techniques of layout and controlling procedures together with the growing trend to applying digital execution included in analog techniques
The input is compared by binary comparator in traditional PulseWidth Modulation (PWM) architectures together with the counter output signal and resetting the Set-Reset flip-flop alike, thereby producing varying duty cycle
A new Digital Pulse Width Modulator (DPWM) structure was introduced in this study is to restrain the DC-DC converter

Summary

Introduction

Current research tasks focused on boosting stable state along with the dynamic behaviour of DC-DC converters for high-performance, by signaling different techniques of layout and controlling procedures together with the growing trend to applying digital execution included in analog techniques. The more the switch will be on than the off stages, more complex will be the power provided towards the loading. Even PWM works nicely for controllers, due to its off/on character, quickly will situate the required duty cycle. It has been applied in some specific communication methods in which its duty cycle was used to communicate information over a communications channel. Like every sort of energy conversion, PWM drivers or related loads need to be tested and designed to satisfy particular performance and efficacy standards but given the sophistication of waveforms connected with PWM application, precise measurement isn’t a very simple job[3]

Proposed Architecture

Result

Conclusion and Future Scope