FOWLP Thermal Debonding: Easing Manufacturing Constraints

Abstract

Fan-out wafer level packaging enables System-in-package (SiP) and other forms of heterogenous integration. Multi-die configuration or passives for SiP alters the warpage profile of the wafer significantly. Wafers with square-shaped dies typically have bowl or dome type deformations. Wafers with rectangular-shaped dies tend to be deformed in a parabolic shape. However, as the packaging advances to different and more sophisticated technologies, the different chip sizes in one wafer adds complexity to the base structure, which leads to an unpredictable warpage profile and a higher warpage magnitude. Downstream equipment post wafer reconstruction needs to be able to handle this change in magnitude and profile since this could otherwise cause difficulties in high volume production and result in lower yield. The process step that requires the wafer to be placed onto chucks will result in vacuum failure and, if not modified to handle high warpage, the transport mechanism can result in wafer excursion and machine downtime. However, these modifications would require a costly redesign of the machine transport system, handling system, and end effectors. A less cost-intensive solution would be to ensure that the incoming wafer post reconstruction has minimum warpage. Thermal debonding is the last process of the wafer reconstruction flow and it acts as launchpad for layer build-up. It is in this step that warpage is inevitable as the wafer is released from the carrier. Thus, it is essential to have a warpage level that is manageable by these succeeding processes. This paper addresses the issue of warpage in Fan-out Wafer Level Packaging and presents a solution that lessens the warpage in the thermal debonding stage. The efficient processing of warped wafers is critical for the development of Fan-out and the transition to high volume manufacturing of these chips.