Abstract

A new noise-shaping architecture for successive approximation register (SAR) analog-to-digital converters (ADCs) was proposed. It does not require comparator modification, so the standard comparator can be used. A first-order noise transfer function with zero located nearly at one can be achieved. This allows the use of higher over sampling ratios (OSR) and increased effective number of bits (ENOB). The architecture is fully passive. The architecture was applied to the design of a 9.9-bit ENOB SAR ADC in a 65 nm complementary metal-oxide semiconductor (CMOS) of United Microelectronics Corporation (UMC) with OSR equal to 10. A 6-bit DAC was used. The proposed architecture provides 3.9 additional bits in ENOB. Signal-to-noise and distortion ratio (SINAD) of 61.4 dBFS was achieved according to simulation results for a signal bandwith of 200 kHz with sampling rate of 4 MS/s.

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