SAR ADC Architecture with Fully Passive Noise Shaping

Abstract

A new fully passive noise-shaping architecture for successive approximation register (SAR) analog-to-digital converters (ADCs) was proposed. A first-order noise transfer function (NTF) with zero located nearly at one can be achieved. The additional pole increases the efficiency of noise shaping to further 3 dB. So, the use of higher over sampling ratios (OSR) and increased effective number of bits (ENOB) is possible. The architecture was applied to the design of a 9.8-bit ENOB SAR ADC in a 65 nm complementary metal-oxide semiconductor (CMOS) of United Microelectronics Corporation (UMC) with OSR equal to 10. A 6-bit capacitive DAC was used. The proposed architecture provides 3.8 additional bits in ENOB. The equalent input bandwitdth is equal to 200 kHz with the sampling rate equal to 4 MS/s.