Finding a Happy Medium for Heterogeneous Cache Integration using M-Series Fan-out Technology

Abstract

For high performance computing, it is desirable to disintegrate the cache memory from the monolithic SoC and reintegrate it through heterogenous integration technologies. Relocating the cache out of the monolithic SoC leads to the reduction of the advanced silicon die size leading to higher yield and lower cost. In this study, we evaluate ways to bridge the gap between high-end 3D silicon interconnect solutions and low-end substrate solutions with Deca’s molded M-Series™ embedded cache fan-out solutions. Deca’s M-Series Chips First Face up FOWLP planarized structure is an ideal platform to build an embedded interposer for the heterogenous integration of the processor chiplets, cache memory, and deep trench capacitors. Deca’s Adaptive Patterning® allows for scaling to high density interconnect between the processor chiplet and the cache memory. Three different configurations of the embedded cache interposer are considered. The vertically stacked face-to-face configurations minimize the interconnect length between the processor and the cache, while the lateral configuration provides a copper to copper build up interconnect between the chiplet and cache enabling further scaling down of the interconnect pitch. Both configurations have their specific benefits and disadvantages which are described in detail in this work.