Femto power-delay(FPD)super threshold level shifter for network on chip (NoC)

Abstract

ABSTRACT This paper presents a novel architecture of femto power-delay super threshold voltage level shifter (LS) for network on-chip voltage control, developed using feedback topology for error aware interconnections data transmission. The proposed LS utilises eight MOS transistors with low aspect ratios for level up or level down. The developed LS can shift as low as 0.12–1.25 V with a tremendous reduction in delay and power consumption. Implemented in 65 nm CMOS technology, the post-layout simulation substantiates the achievement of voltage translation. The proposed LS incurs energy per cycle of 44 fJ during up shift; the average of level up and level down static power consumption is 3.61 nW, while VDDL is 0.3 V and VDDH is 1.2 V at a frequency of 1 MHz. The layout area of the proposed LS is 3.21 µm × 2.13 µm.