High speed energy efficient level shifter for multi core processors

Abstract

The energy efficiency and power consumption are the two primary and major concerns in present emerging applications like miniaturized bio medical sensors, pace makers, multimedia processors, etc. The energy and power consumption may decreases by multiple ways. The multiple power supply voltage design is an efficient and dominant technique for the reduction of energy and power consumption at processor level. The multi core processors uses level shifters and this level shifter may become burden, when its own energy and power consumption is high, at the same time there is area overhead also. In this paper a high speed Energy efficient level shifter circuit is proposed that performs level up shifting & Level down shifting. The design is designed & simulated using 90nm model files. The proposed one is a unique design, is encompass a level shifter and provision for auto selection of type of shift (Level up/Level down). The proposed level shifter strength has study at signal frequency of 1 MHz, 500 KHz, and 100 KHz with a load capacitance variation from 10fF-60fF. The proposed design has an average delay of 2.8 ns & power consumption is 36.4 nW at 0.4V VIN and 0.18 ns & 16 nW at IV VTN.