Low-Power Deep-Submicron CMOS Adder Using Optimized Delay Universal Gates

Abstract

Scaling down of CMOS technology requires vital reduction of leakage power in low-power applications. Power gating technique is generally employed in the standby mode to reduce static power consumption but it increases delay of the logic cells badly and the ultimate result of the circuit is besmirched to a great extent in deep submicron circuits. This paper utilizes feedback mechanism for reducing dynamic and static power during active and standby mode, respectively, and power gating technique is also engaged for further minimizing static power during standby mode. Novel optimal power gates such as NOT, NAND, NOR, and EX-OR are developed and simulations are done with 45 nm CMOS technology and 0.6 V supply voltage for the 32-bit ripple carry adder. Proposed adder using optimal power NAND gate accomplishes 46 percent reduction in dynamic power consumption and 84.3 percent reduction in static power consumption and 28.98 percent reduction in power delay product.