Output load capacitance based low power implementation of UART on FPGA

Abstract

Core dynamic power is independent of output load capacitance. IO power and static power is dependent on output load capacitance. In this work, we achieved 99.72% reduction in IOs power consumption of Universal Asynchronous Receiver Transmitter (UART) if we scale down output load from 10,000pf to 5pF in IOB setting of FPGA. Universal Asynchronous Receiver and Transmitter are a transceiver circuits that transmit/receive data between parallel and serial forms and vice versa. Design state of our design is high because no black box found. Bit width is high because 57.6% of primitives in RTL net list represent 1-bit logic. Here, IO power consumption is 17,226mW on 10,000pF output load which significantly reduce to 47mW on 5pF output load. Along with reduction in IOs power, we also observed 24.5% reduction in static power consumption from 1322mW on 10,000pF output load to 1004mW on 5pF output load. In our implementation on FPGA, we take Virtex-6 family, XC6VLX75T device, FF484 package, −1 speed grade, XST synthesis tool, ISim simulator, and Verilog as preferred HDL language.