Features of phonon-limited electron mobility behavior of double-gate field-effect transistor with (111) Si surface channel

Abstract

One-dimensional self-consistent calculations and relaxation time approximations are used to study the phonon-limited electron mobility of the inversion layer at room temperature for ultrathin body Si (111) layers in single-gate (SG) and double-gate (DG) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFET’s). Assuming a 5-nm-thick SOI layer, it is shown that intravalley phonon scattering (acoustic-phonon scattering) in the DG SOI MOSFET inversion layer is strongly suppressed within a range of medium effective field (Eeff) values; DG SOI MOSFETs have higher phonon-limited electron mobility than SG SOI MOSFET’s. Many simulations strongly suggest that the suppression of acoustic-phonon scattering in a 5nm TSOI DG SOI MOSFET primarily stems from the reduction of the form factor (F00) value within medium Eeff values.