Empirical Models of Phonon-Limited Electron Mobility for Ultrathin-Body Single-Gate and Double-Gate Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors with (001) or (111) Si Surface Channel

Abstract

We propose empirical models of the phonon-limited electron mobility of single-gate (SG) and double-gate (DG) silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) with (001) or (111) Si surface channels. Electron mobility models are functions of the SOI layer thickness and the effective electric field. The proposed phonon-limited electron mobility models accurately reproduce self-consistent simulation results. The purpose of the study is to produce reliable mobility models that can be applied to commercial device simulators. Using the electron density derived from quantum simulations and the proposed empirical electron mobility models, drain current vs gate voltage (Id–Vg) and transconductance vs gate voltage (gm–Vg) characteristics of SG and DG SOI MOSFETs with 10- and 3-nm-thick SOI layers, (001) or (111) surfaces, are calculated to examine the potential of the proposed mobility models. The results are compared with commercial two-dimensional (2-D) device simulation results (DEESIS simulator). It has been shown that the DESSIS results are not reliable when the device has a sub-10-nm-thick SOI layer. The proposed model, on the other hand, clearly reproduces the effects of Si surface orientation and device structure. The proposed models are useful for a simple estimation of the drive current of various SOI MOSFETs and for reducing the computation time in device simulations and circuit simulations.