Impact of Phonon-Limited Mobility Superiority in Double-Gate or Fin FET with a (111) Si and (001) Ge Surface Channel on Device Scaling

Abstract

1D self-consistent calculations and relaxation time approximations are used to study the phonon-limited electron mobility of the inversion layer at room temperature for ultra- thin Si (111), Ge (001) and Ge (111) layers in single-gate (SG) and double-gate (DG) MOSFET's. Assuming a 5-nm-thick SOI layer, it is shown that intra-valley phonon scattering in the DG SOI MOSFET inversion layer is strongly suppressed within a range of medium Eeff value; DG devices have higher phonon- limited electron mobility than SG devices. The suppression of intra-valley phonon scattering in a 5-nm TSOI DG device primarily stems from the reduction of the form factor (F00) value within medium Eeff values. Similar aspects of electron mobility expected for SG and DG GOI MOSFET's are also discussed.