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Abstract
Bipolar Emitter Coupled Logic (ECL) devices can now be fabricated at higher densities and consumes much lower power. Behaviour of simple and complex ECL gates are examined in the presence of physical faults. The effectiveness of the classical stuck-at model in representing physical failures in ECL gates is examined. It is shown that the conventional stuck-at fault model cannot represent a majority of circuit level faults. A new augmented stuck-at fault model is presented which provides a significantly higher coverage of physical failures. The model may be applicable to other logic families that use logic gates with both true and complementary outputs. A design for testability approach is suggested for on-line detection of certain error conditions occurring in gates with true and complementary outputs which is a normal implementation for ECL devices.
Highlights
Emitter Coupled Logic (ECL) using bipolar technology is a non-saturated form of digital logic which eliminates transistor storage time as a speed limiting characteristic, permitting very high speeds of operation [q ]
An augmented stuck-at fault model has been proposed as the classical stuck-at fault model did not model a major fraction of the physical failures
High fault coverage can be obtained using the augmented stuck-at fault model for ECL gates compared to the classical stuck-at fault model
Summary
Emitter Coupled Logic (ECL) using bipolar technology is a non-saturated form of digital logic which eliminates transistor storage time as a speed limiting characteristic, permitting very high speeds of operation [q ]. Transistor level shorts and opens model a majority of the physical failures and defects in ICs [4,5]. Analysis of faults in simple logic circuits suggest that transistor level testing provides a higher coverage of faults compared to that at gate level 16]. Modeling and analysis of bridging faults in Emitter Coupled Logic devices were presented in [20] and [21]. We propose an augmented stuck-at fault model which provides a higher coverage of physical failures, and extend this philosophy to a 2-level complex ECL gate.
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