Abstract
Simple analytical expressions for the ECL (emitter coupled logic) gate delays are proposed and applied to typical ECL gates using Si and SiGe epitaxial base bipolar transistors, and their accuracy is demonstrated. By studying some of the tradeoffs existing between some of the parameters, it is shown how such a simple analysis can be helpful for adjusting the parameters of the transistors to the optimum values, rather than systematically having to push the technology to the limit. >
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