Highly accurate and simple models for CML and ECL gates

Abstract

In this paper simple and accurate models for the propagation delay of both current mode logic (CML) and emitter-coupled logic (ECL) gates are proposed. The models start from the small signal model properly evaluated. This makes it possible to represent propagation delay with a few terms, providing a better insight into the relationship between delay and its electrical parameters, which in turn are related to process parameters. The main difference between accurate and simple models is that the former need few Spice simulations to properly evaluate the model parameters. In order to validate the models, a comparison using both a traditional and a high-speed bipolar process was carried out under many bias conditions and output loads. Simple models have typical errors of around 20%. Accurate models have typical errors as low as 2% and 5% for CML and ECL, respectively, while the worst case error is as low as 5% and 8% for CML and ECL, respectively.