Abstract
In this paper a pencil-and-paper optimized design for current mode logic (CML) and emitter coupled logic (ECL) gates is proposed. The approaches are based on simple models which show errors lower than 20% as compared with Spice simulations. The optimization is performed in terms of bias currents, which give the minimum propagation delay, and it is demonstrated that at the cost of a 10% increase in propagation delay we can reduce the power dissipation by 40%. Strategies to optimize the transistor area of the CML gates are also discussed. A comparison between the optimized CML and ECL, is made. It shows the advantage of the CML gate with respect to the ECL, in terms of propagation delay. However, this feature of CML is paid for in terms of power dissipation. The simple models and the design strategies are validated by using both a traditional and a high-speed bipolar process, which have transition frequencies equal to 6 and 20 GHz, respectively.
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