Abstract
This paper presents modeling and optimized design of Current Mode Logic (CML) MUX. Propagation delay models with few terms are presented. The most accurate model has errors lower than 2%. By using the proposed models a design optimization is proposed. In particular, the bias currents which gives the minimum propagation delay are found. Moreover, it is demonstrated that at the cost of a 10% increase in propagation delay a 40% reduction in the power dissipation can be achieved. The models and design strategies are validated using both a traditional and a high-speed bipolar process which have a transition frequency equal to 6 GHz and 20 GHz, respectively.
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