Abstract
Modern large‐scale circuit designs have created great demand for fast and high‐quality global routing algorithms to resolve the routing congestion at the global level. Rip‐up and reroute scheme has been employed by the majority of academic and industrial global routers today, which iteratively resolve the congestion by recreating the routing path based on current congestion. This method is proved to be the most practical routing framework. However, the traditional iterative maze routing technique converges very slowly and easily gets stuck at local optimal solutions. In this work, we propose a very efficient and high‐quality global router—FastRoute. FastRoute integrates several novel techniques: fast congestion‐driven via‐aware Steiner tree construction, 3‐bend routing, virtual capacity adjustment, multisource multi‐sink maze routing, and spiral layer assignment. These techniques not only address the routing congestion measured at the edges of global routing grids but also minimize the total wirelength and via usage, which is critical for subsequent detailed routing, yield, and manufacturability. Experimental results show that FastRoute is highly effective and efficient to solve ISPD07 and ISPD08 global routing benchmark suites. The results outperform recently published academic global routers in both routability and runtime. In particular, for ISPD07 and ISPD08 global routing benchmarks, FastRoute generates 12 congestion‐free solutions out of 16 benchmarks with a speed significantly faster than other routers.
Highlights
As the feature size of modern VLSI design continues to shrink and the on-chip communication becomes extremely complicated, the ascending circuit density poses greater challenges for VLSI routers
Modern designs are liable to congestion problems due to increasing on-chip communication, concentrated routing demands and limited routing resources
While 3bend routing offers a new degree of balance among congestion reduction, via generation and runtime, multi-source and multisink maze routing relaxes a major constraint on traditional maze routing and greatly improves the quality of global routing
Summary
As the feature size of modern VLSI design continues to shrink and the on-chip communication becomes extremely complicated, the ascending circuit density poses greater challenges for VLSI routers. The negotiationbased cost functions are used by maze routing to drive the nets away from consistently congested regions In both ISPD 2007 and ISPD 2008 global routing contests, 3-dimensional benchmarks include the costs on vias for performance evaluation to encourage the global routers to consider the via effect. The second and third contributions focus on the optimization of tree structure before any actual routing They can improve the routing quality of nets in congestion free region and effectively reduce the runtime for the actual routing process. While 3bend routing offers a new degree of balance among congestion reduction, via generation and runtime, multi-source and multisink maze routing relaxes a major constraint on traditional maze routing and greatly improves the quality of global routing.
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