FastRoute: A Step to Integrate Global Routing into Placement

Abstract

Because of the increasing dominance of interconnect issues in advanced IC technology, placement has become a critical step in the IC design flow. To get accurate interconnect information during the placement process, it is desirable to incorporate global routing into it. However, previous global routers are computationally expensive. It is impractical to perform global routing repeatedly during placement. In this paper, we present an extremely fast and high-quality global router called FastRoute. In traditional global routing approaches, congestion is not considered during Steiner tree construction. So they have to rely on the time-consuming maze routing technique to eliminate routing congestion. Different from traditional approaches, we proposed a congestion-driven Steiner tree topology generation technique and an edge shifting technique to determine the good Steiner tree topologies and Steiner node positions. Based on the congestion-driven Steiner trees, we only need to apply maze routing to a small percentage of the two-pin nets once to obtain high quality global routing solutions. We also proposed a new cost function based on logistic function to direct the maze routing. Experimental results show that FastRoute generates less congested solutions in 132times and 64times faster runtimes than the state-of-the-art academic global routers Labyrinth (R. Kastner et al, 2000) and Chi Dispersion router (R. T. Hadsell and P. H. Madden, 2003), respectively. It is even faster than the highly-efficient congestion estimator FaDGloR (J. Westra and P. Groeneveld, 2005). The promising results make it possible to incorporate global routing directly into placement process without much runtime penalty. This could dramatically improve the placement solution quality. We believe this work will fundamentally change the way the EDA community look at and make use of global routing in the whole design flow