Extended-$\hbox{p}^{+}$ Stepped Gate LDMOS for Improved Performance

Abstract

In this brief, we propose a new extended-p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> stepped gate (ESG) thin-film silicon-on-insulator laterally double-diffused metal-oxide-semiconductor (LDMOS) with an extended-p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> region beneath the source and a stepped gate structure in the drift region of the LDMOS. The hole current generated due to impact ionization is now collected from an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> - p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> junction instead of an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -p junction, thus delaying the parasitic bipolar junction transistor action. The stepped gate structure enhances RESURF in the drift region and minimizes the gate-drain capacitance. Based on 2-D simulation results, we show that the ESG LDMOS exhibits approximately 63% improvement in breakdown voltage, 38% improvement in on-resistance, 11% improvement in peak transconductance, 18% improvement in switching speed, and 63% reduction in gate-drain charge density compared with the conventional LDMOS with a field plate.