In0.53Ga0.47As/In0.52Al0.48As Quantum Well Step Gate LDMOS to Improve the Device Performance

Abstract

In this work, a new laterally double diffused metal oxide semiconductor (LDMOS) using In0.53Ga0.47As/In0.52Al0.48As Quantum well (QW) layer with a p-well step gate has been proposed. In the proposed device structure, the gate region splits into three steps in which the oxide thickness increases from the source to the drain end. As the gate insulator width varies from source to drain end, it results in better control of the gate over the channel and also a reduction in the gate-to-drain capacitance (CGD). These features offer higher transconductance with reduced switching delays, which makes the device appropriate for RF applications. Again, the concentration of current in the channel section is enhanced due to the presence of the Quantum well region and the InP spacer layer, which drastically reduces the On-resistance. But, the device achieves lesser gate-to-drain capacitance which results in decrease in the switching speed. On the other hand the proposed device offers less gate charge with the low value of CGD gives minimised switching loss. Based on 2D TCAD simulation, the proposed QW LDMOS exhibits 70% improvement in On-resistance, 45% in breakdown voltage, 84% improvement in peak transconductance, 26% improvement in switching delay, and 19% improvement in gate charge density as compared to conventional In0.53Ga0.47As devices.