A new SiGe Stepped Gate (SSG) thin film SOI LDMOS for enhanced breakdown voltage and reduced delay

Abstract

This paper introduces a new SiGe Stepped Gate (SSG) thin film SOI LDMOS for enhanced performance. The proposed device eliminates the premature breakdown of the device due to floating body effects, which is one major problem of the thin film SOI LDMOS. The most common technique used to eliminate the floating body effects in SOI power device is the source tied body contact. Though this technique is successful in thick film devices, its effectiveness to thin film LDMOS is questionable, and also it imposes area penalty. Without a body contact, the floating body effects can be also reduced by decreasing the drift region doping [1]. But increased drift region resistance degrades the on-resistance of the device. The proposed device, SSG LDMOS circumvents the above challenges. It has a germanium implanted source and stepped field plate in the drift region. The SSG LDMOS reduces floating body effects in two ways. The SiGe source offers low potential to the excess holes generated due to the impact ionization [2]. The stepped gate reduces gate-drain capacitance improving the switching speed. The combined effect of (i) SiGe in the source and (ii) the stepped gate, improves the breakdown voltage and also allows us to increase the drift doping levels resulting in a reduced on-resistance. Using two dimensional device simulation [3], the proposed device is simulated and compared with the conventional thin film LDMOS. The cross-sectional view of both the devices is shown in Fig. 1. The conventional LDMOS has a uniform gate oxide thickness of 50 nm with a field plate. The drift region doping in both the devices is chosen for maximum breakdown voltage and is found to be 9×10 16 cm -3 (which is higher than the conventional device doping 3×10 16 cm -3 ). The germanium mole fraction in the SiGe source of the SSG LDMOS is chosen to be 0.2. The device parameters used in our simulation are given in Table 1. Figs. 2 and 3 show the breakdown characteristics and the on-resistance variation of the SSG LDMOS and the conventional LDMOS. The SSG LDMOS exhibits a 97% improvement in breakdown voltage and a 61% reduction in onresistance compared to the convetional LDMOS. Figs. 4 and 5 show the switching delay and the gate-charge behaviour. We observe that the SSG LDMOS exhibits a 57% reduction in switching delay and a 50% reduction in gate-drain charge compared to the conventional LDMOS. This work clearly demonstrates the application of SiGe source and a stepped oxide gate in improving the performance of the LDMOS making this device more useful in both RF and wireless system-onchip applications.