Exploiting Heterogeneity in Cache Hierarchy in Dark-Silicon 3D Chip Multi-processors

Abstract

Technology scaling has enabled increasing number of cores on a chip in Chip-Multiprocessors (CMPs). As the number of cores increases, the overall system will need to provide more cache resources to feed all the cores. However, increasing the size of each cache level in the cache hierarchy of CMPs mitigates the large off-chip memory access latencies and bandwidth constraints. Moreover, cache hierarchy is known as one of the most power-hungry components in many-core CMPs because leakage power within the cache systems has become a significant contributor in the overall chip power budget in deep sub-micron as well as dark silicon era. Due to the many advantages of Non-Volatile Memory (NVM) technology such as high density, near zero leakage, and non-volatility, in this paper, we focus on exploiting such memories in the cache hierarchy. Specifically, we focus on 3D CMPs to decrease the leakage power consumption and mitigating the dark silicon phenomenon. Experimental results show that the proposed method on average improves the throughput by 45.5% and energy-delay product by 56% when compared to the conventional single cache technology.