Energy efficient 3D Hybrid processor-memory architecture for the dark silicon age

Abstract

With increasing the number of cores on the Chip-Multiprocessors (CMPs) as a result of continuous technology scaling, more cache resources are needed to feed all the cores. Hence, in order to improve performance by reducing off-chip memory access, inevitably on-chip caches should be increased. In on-chip cache hierarchy, last level cache (LLCs) is the largest one consuming more energy compared with the other levels in many-core CMPs as leakage power within the LLC has become a significant contributor in the overall chip power budget in deep sub-micron as well as dark silicon era. In this paper, we focus on exploiting Non-Volatile Memory (NVM) which is a new type of memory with promising features in shared distributed LLCs to decrease the leakage power consumption and mitigating the dark silicon phenomenon. In our proposed strategy, we first calculate Average Memory Access Time (AMAT) of running applications on the CMP in each predetermined interval by collected systems memory traffic. Based on the monitored AMATs, we then adaptively reconfigure Hybrid distributed LLC by selecting the proper memory type (i.e., SRAM bank or STT-RAM bank) at runtime. Experiment results on the PARSEC benchmarks show that the proposed method provides up to 55.22% (on average 39.3%) energy reduction and 35.33% on average energy-delay product (EDP) improvement with only 6% performance degradation compared to the conventional methods where single cache technology is used.