Abstract
This paper addresses a set of design paradigms by exploiting device and architectural heterogeneity to mitigate the dark silicon. We exploit Non-Volatile Memory (NVM) as potential replacements to conventional caches. Also, we study the problem of dynamic thread mapping in future Chip Multi-Processors (CMPs) via an efficient scheduler. Evaluations on a 3D architecture consisting of 8 core (a big and a small core on each tile) show that the proposed method provides up to 7% average performance improvement for multithreaded benchmarks, and 9% for multiprogrammed workloads. The results also show 62.5% and 67.7% on average energy-delay product (EDP) improvement for multithreaded and multiprogrammed workloads respectively, with 7.87% area overhead compared to the conventional methods.
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