Abstract
An engineering change orders design using multiple variable linear programming for VLSI design is presented in this paper. This approach addresses the main issues of resource between spare cells and target cells. We adopt linear programming technique to plan and balance the spare cells and target cells to meet the new specification according to logic transformation. The proposed method solves the related problem of resource for ECO problems and provides a well solution. The scheme shows new concept to manage the spare cells to meet possible target cells for ECO research.
Highlights
Engineering change orders (ECO) are important technologies used for changes in integrated circuit (IC) layout and compensate for design problems
Are there enough spare cells and types to satisfy the consumption of patch logic? How to estimate the quantity and logic types of ECO procedure? In order to solve this problem, we proposed an engineering change orders design using multiple variables linear programming for VLSI design in this paper
Before discussing the engineering change orders design using multiple variables linear programming, we addressed ECO logic transformation
Summary
Engineering change orders (ECO) are important technologies used for changes in integrated circuit (IC) layout and compensate for design problems. To perform the ECO, IC designers adopt sprinkling many unused logic gates during IC design flow. In order to perform ECO efficiently, literature [4,5,6,7,8,9] adopt minimal change EC equations automatically. Lin et al addressed logic synthesis techniques for engineering change problems [6]. Watanabe and Brayton presented another kind of incremental synthesis technique for engineering changes [9]. In order to solve the problems, we adopt linear programming technique to plan and balance the spare cells and target cells in this paper. The proposed scheme meets the new specification according to logic transformation and overcomes the related problems of resource for ECO research.
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