Efficient threshold logic in 1T1R array

Abstract

In-memory computing based on memristor logic is one of the most promising approaches to break the ‘memory wall’ and ‘power wall’. However, some important logics (such as AND and MAJ) cannot be implemented efficiently in 1T1R arrays, which makes it difficult to design low-delay memristor-based logic computing systems. An efficient threshold logic is proposed by adding an auxiliary memristor in MAGIC (N+1)-OR gate and optimising the driving voltage. The proposed threshold logic can be completely implemented in a 1T1R array without any additional resistor, and can achieve AND logic and MAJ logic directly. Furthermore, a 1-bit full adder based on the proposed threshold logic, which only requires three steps and six memristors, is designed. Our proposed threshold logic and full adder design perform advantages in terms of area and delay compared with the previous designs.