Abstract
In-memory computing based on memristor logic is one of the most promising approaches to break the ‘memory wall’ and ‘power wall’. However, some important logics (such as AND and MAJ) cannot be implemented efficiently in 1T1R arrays, which makes it difficult to design low-delay memristor-based logic computing systems. An efficient threshold logic is proposed by adding an auxiliary memristor in MAGIC (N+1)-OR gate and optimising the driving voltage. The proposed threshold logic can be completely implemented in a 1T1R array without any additional resistor, and can achieve AND logic and MAJ logic directly. Furthermore, a 1-bit full adder based on the proposed threshold logic, which only requires three steps and six memristors, is designed. Our proposed threshold logic and full adder design perform advantages in terms of area and delay compared with the previous designs.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
