Abstract

Very large-scale integration technology is accelerating the growth and prevalence of nanoscale devices worldwide, but at the same time facing technical challenges in terms of fault detection due to the compact size of chips. Thus, the detection of faults in chips caused by limitations of the manufacturing process or operational aspects of the architecture is obligatory to assess the effective performance of devices. In this paper, two single-ended ring oscillator (SERO)-based transistor stuck-on (TSON) fault detection methods are proposed for complementary metal–oxide–semiconductor (CMOS) circuits. The SERO is used as a current-controlled and voltage-controlled oscillator in method 1 and 2, respectively, reducing the circuit overhead of the detection block. Simulations are carried out using Cadence Virtuoso in 90-nm technology. The results show that both methods can successfully detect TSON faults in CMOS circuits based on the oscillatory behavior of the SERO. Moreover, these methods avoid the need to sense the output voltage level or quiescent current, which increases the possibility of successful fault detection, especially for submicron-level structures by avoiding improper logic and unreliable current values. Test vectors and fault locations can also be easily identified using the proposed methods, reducing the implementation complexity of CMOS fault detection techniques.

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