Effects of source/drain elevation and side spacer dielectric on drivability performance of non-abrupt ultra shallow junction gate underlap GAA MOSFETs

Abstract

Present work focuses on quantitative effects of source/drain elevation height ( $${\text{h}}_{\text{SD}}$$ ) and side spacer dielectric material (Air, SiO2, Si3N4 and HfO2) on the current drive of non-abrupt ultra shallow junction (USJ) gate all around (GAA) MOSFETs. It has been observed that the desirable unanimous reverse trend (increase in $${\text{I}}_{\text{on}}$$ and decrease in $${\text{I}}_{\text{off}}$$ with increase in source/drain elevation height ( $${\text{h}}_{\text{SD}}$$ ) and/or side spacer dielectric constant, $$\upvarepsilon_{\text{sp}}$$ ). Utmost percentage improvement in $${\text{I}}_{\text{on}} /{\text{I}}_{\text{off}}$$ ratio at $${\text{h}}_{\text{SD}} = 30.5\,{\text{nm}}$$ and $$\sigma_{\text{L}} = 7\;{\text{nm}}$$ is found to be ~3000% for HfO2 while least as ~449% for Air with respect to their corresponding values at zero elevation. Thus, the increase in source/drain elevation with proper selection of side spacer is found to be a suitable approach. This will enhance the drivability as well as lower parasitic resistance in comparison to non elevated GAA MOSFETs at sub 20 nm technology node.