Abstract
We have demonstrated the effects of interface traps and defects on the charge retention characteristics in silicon-quantum-dot (Si-QDs)-based metal-oxide-semiconductor (MOS) memory structures. MOS diodes with various interface traps and defects introduced by thermal annealing treatment are investigated using a capacitance-voltage (C-V) measurement technique. The model of deep trapping centers including three-dimensional quantum confinement and Coulomb charge effects has been developed to successfully explain the observed long-term charge retention behaviors.
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