Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

Abstract

We have studied the effect of top gate bias (VTG) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm2 intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the VTG from −15 to +15 V. By changing VTG from negative to positive, the Fermi level (EF) shifts toward conduction band edge (EC), which substantially controls the conversion of neutral vacancy to charged one (VO → VO+/VO2+ + e−/2e−), peroxide (O22−) formation or conversion of ionized interstitial (Oi2−) to neutral interstitial (Oi), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows −2.7 V shift at VTG = −15 V, which gradually decreases to −0.42 V shift at VTG = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (VO+/VO2+/O22−/Oi) and/or hole trapping in the a-IGZO /interfaces.