Abstract
The effects of drain-induced barrier lowering (DIBL) on the performance characteristics of devices and circuits operating in the subthreshold region are evaluated by measurement and simulation. It is found that the measured drain current markedly decreases in the presence of a large DIBL at supply voltage (Vdd) in the subthreshold region such as 0.3 V. In addition, the simulated propagation delay of ring oscillators is more degraded in the subthreshold region as DIBL increases even though the on-current (Ion) is the same in all the devices, and the calculated energy consumption increases with DIBL in the subthreshold region. It is concluded that DIBL should be suppressed in the design of subthreshold CMOS circuits.
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