Dynamic performance of graded channel DG FD SOI n-MOSFETs for minimizing the gate misalignment effect

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Double gate MOSFET has been regarded as the most promising candidate for future CMOS devices, for excellent short channel effects (SCEs) immunity and high current drivability due to double gate coupling. The alignment between the top and bottom gates should be concern to fully realize the benefits of the double-gate configuration, as gate misalignment causes degradation in the device performance. Use of graded channel architectures somehow reduces the effect of gate misalignment. We scrutinize that how the misalignment affects the small signal behavior and device characteristics like conductances, capacitances and cut-off frequency, for uniformly doped and graded channel double gate architectures. Considering the fact that gate misalignment can occur on any side of the gate, extensive simulations have been carried out using high–low (H–L), low–high (L–H) and low–high–low (L–H–L) doping profiles for both source (DGS) and drain side (DGD) gate misalignment.