Dopant diffusion in [formula omitted] poly gate CMOS process

Abstract

n + p + Poly gate CMOS devices were fabricated by a process modified from the “Twin-Tub V” CMOS ( n + poly gate) processing technology, using source-drain implants for polysilicon doping. CMOS devices so fabricated show comparable characteristics to devices fabricated by the Twin-Tub V process. The effect of dopant diffusion, both vertical and lateral, was studied in terms of several S/D implant anneal temperatures, 850–950°C. After high-temperature anneal, boron penetration from gate to the silicon resulted in depletion-mode characteristics in the p channel device. Lateral diffusion was observed for all processing conditions used. However, it was shown that when p + and n + poly gates are doped homogeneously above the degenerate level, the compensation effect from the counter doping by the diffused-in dopant does not cause measurable variations in the threshold voltage.