Direct Digital Frequency Synthesizer design with non-uniform squared-sine-weighted Digital-to-Analog Convertor

Abstract

In this paper, a novel Direct Digital Frequency Synthesizer (DDFS) based on using squared-sine-weighted Digital-to-Analog Convertor (DAC) is proposed. To increase the speed, parallel DACs with Return-To-Zero (RTZ) technique are used. In the conventional DDFSs for generating signal, a phase to sine mapper (PSM) is used, that often includes a look-up table memory. Because of the speed and area bottleneck of the look-up table memory, sine-weighted-DAC is used. Generating sampled-data signals near the Nyquist rate frequency requires a sharp smoothing filter. For avoiding requiring a sharp filter and generating signals beyond the Nyquist rate, parallel DACs and RTZ technique are used that causes speed relaxation in single DACs. To reduce area and power, non-uniform segmentation by modifying the conventional sine weighted DAC is proposed. Also using square-sine instead of sine ignores the need of extra Gilbert cell in DDFS for generating negative parts of the sine wave. The Non-uniform segmentation reduces about %26.52 chip area of DACs and nearly the same amount of reduction in consumed dynamic power. In the simulation with 0.18μm CMOS process with an external clock frequency of 2GHz, the DDFS with 8-bit frequency resolution generate output sinusoidal signal of 968.75 MHz frequency, to see the worst case, giving a Spurious Free Dynamic Range (SFDR) of 67.41 dB.