A 9-bit, 1-giga samples per second sine and cosine direct digital frequency synthesizer

Abstract

A 9-bit phase and 8-bit amplitude resolutions CMOS direct digital frequency synthesizer (DDFS) is presented that gives sine and cosine outputs simultaneously. In addition two 10-bit on-chip digital to analog converters (DAC) was used to make the final sine/cosine analog output voltages. In the proposed DDFS we developed a new structure for the ROM section that makes it to give us the sine and cosine digital output signals simultaneously by used of just one lookup table in an efficient way. Thus the DDFS circuit occupies less silicon area and as a result it has less power dissipation in contrast with the similar works. All of the circuits designed in 0.35μm CMOS technology. The complete layout of the system was drawn by Cadence software and its extracted simulation shows very good results of the sine/cosine outputs. A 9-bit frequency control word gives a tuning resolution of 1.95-MHz at a 1-GHz sampling rate with 2-clock frequency switching latency. The occupied total silicon area for the DDFS and two DACs is about 2.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the power consumption of them is about 186 mW at a clock frequency of 1GHz. The spurious-free dynamic range (SFDR) is 55 dBc at low synthesized frequencies. The power efficiency figure-of-merit (FOM) of this chip is the best reported of 2446 in the mm-wave DDS design.