High-frequency Direct Digital Frequency Synthesizer design with non-uniform sine-weighted Digital-to-Analog Convertor

Abstract

In this paper, a novel Direct Digital Frequency Synthesizer (DDFS) based on using non-uniform segmentation in sine-weighted Digital-to-Analog Convertor (DAC) is proposed. To generating beyond Nyquist frequency signal, parallel DACs with Return-To-Zero (RTZ) technique are used. In conventional DDFSs for generating signal, a Phase to Sine Mapper (PSM) is used that often includes a look-up table memory. Because of the speed and area bottleneck of the look-up table memory, sine-weighted-DAC is used. Generating sampled-data signals near the Nyquist rate frequency requires a sharp smoothing filter. For avoiding requiring a sharp filter and generating signals beyond the Nyquist rate, parallel DACs and RTZ technique are used that causes speed relaxation in single DACs. To reduce area and power, non-uniform segmentation by modified sine weighted DAC is proposed. This technique causes to reduce DACs area by %30.13, and nearly the same amount of reduction in consumed dynamic power. In the simulation in 0.18μm CMOS technology with an external clock output frequency of 2GHz, the DDFS with 8-bit frequency resolution can generate output sine signal of 984.375 MHz frequency, to see the worst case, giving a Spurious Free Dynamic Range (SFDR) of 52.1dB.