Different access mechanisms for set-associative cache architecture for reduced power consumption

Abstract

In recent years, power consumption has become one of the most critical design concern. Due to lower miss rate, set-associative caches are usually employed to improve embedded system's performance. However, a conventional set-associative cache implementation is not power efficient. Thus, in order to achieve low-power consumption, novel set-associative cache architectures have been proposed in which efficient accessing of tag bits and the data bits takes place in two phases unlike the conventional set-associative cache architectures. The behavioural modelling of the cache architectures was done using Verilog Hardware Description Language (HDL). The synthesis results illustrate that the proposed parallel and sequential set-associative cache architectures showed significant power reduction of 34.92% and 35.36% on an average as compared to conventional parallel and conventional sequential set-associative cache architectures, respectively.