Design of an adjustable-way set-associative cache

Abstract

The trade-off between direct-mapped caches and set-associative caches is an important issue in the research on the performance of caches. The conventional set-associative caches with higher associativity provide lower miss rate, however, they suffer from longer hit access time and larger energy consumption. Based on the consideration of different program localities, the different programs should select the caches with the appropriate associativity. In this paper, we propose a set-associative cache that can provide the flexibility to adjust its associativity according to the different program behaviors, which means that the proposed cache scheme can be adjusted from n-way set-associative cache to direct-mapped cache. By this cache architecture, the power consumption will be saved when an n-way set-associative cache configures as the cache with lower associativity (less than n) due to only enabling the fewer subarrays of the tag memory and the data memory. However, the performance is also maintained as the conventional set-associative cache or the direct-mapped cache. In the future, the adjustable-way set-associative cache can be applied to the multiprocessor system to reduce the average energy consumption of the overall system.