Phased set associative cache design for reduced power consumption

Abstract

In this paper, improvised versions of the set associative cache accessing technique have been proposed to reduce the power consumption. In phased cache the cache-access process is divided into two phases. In the first phase all the tag in the set are examined in parallel. In the next phase, if there is a hit, then a data access is performed for the hit way. The average energy consumption is reduced as we are not accessing the data together with tag in each phase. Behavioral implementation of these mechanisms was carried out using Verilog HDL. Synthesis of the design was done in Xilinx 10.1. The Xilinx Xpower analyzer is used to find the power consumption. The results show an average of 41% reduction in power consumption as compared to the conventional sequential set associative cache and an average of 21% power reduction as compared to conventional parallel set associative cache architecture.