Abstract
Pre-bond testing and defect identification of through silicon via (TSV) is extremely important for yield assurance of 3D stacked devices. Based on a recently published pre-bond TSV probing technique, this paper proposes an ILP (integer linear programming) model to generate near-optimal set of sessions for pre-bond TSV test. The sessions generated by our model identify defective TSVs in a TSV network with the same capability as that of other available heuristic methods, but with consistently reduced test time. The ILP model is shown to reduce the pre-bond TSV test time by 38.2% for pinpointing up to two faulty TSVs in an 11-TSV network. Reducing prebond TSV test time helps reduce the manufacturing cost of 3D stacked devices. This ILP model has low complexity and an example demonstration using a commercial solver takes less than 40 seconds.
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