Abstract
Through-silicon via (TSV) based three-dimensional integrated circuit (3D IC) is gaining remarkable attention in semiconductor industry. The design of 3D IC goes through a complex manufacturing process and testing of TSVs is a critical issue to the researchers. This paper presents an efficient solution for pre-bond TSV testing. The proposed method generates the sequence of test sessions for identifying defective TSVs in a TSV network in reduced test time. Simulation results show the effectiveness of proposed method in terms of test time reduction than the prior works.
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