Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testing

Abstract

Through-silicon-Via (TSV) based three dimensional stacked integrated circuits (3D SICs) testing is a promising area in modern days semiconductor industry. It is seen that the yield of 3D SIC depends on interlayer vertical inter-connectors. Imperfection during the fabrication process results in yield-reducing manufacturing defects. Hence, identification of faulty TSVs and recovery of those faulty TSVs are necessary to improve the yield. In this paper, we have proposed a methodology to test the regular TSVs before bonding (pre-bonding) to identify the faulty TSVs uniquely in reduced test time. Our algorithm also performs better in terms of test time reduction than the previous works presented in the literature. This paper also has discussed the idea of recovery of faulty regular TSVs using redundant TSVs. For a given group ratio, the best possible multiple dependent regular TSVs can be achieved using our proposed scheme for redundancy.