Abstract
This paper proposes a DEVS (Discrete Event System Specification) formalism-based approach to analyze Clock Domain Crossing (CDC) issues in digital circuit design. As modern System on Chip (SoC) designs increasingly integrate multiple clock domains, the verification of CDC-related metastability becomes more challenging and costly. While conventional EDA tools offer solutions for CDC analysis, they often involve substantial computational resources and licensing costs. We present a DEVS-based simulation framework that leverages its inherent advantages in time management and modular structuring to model and analyze CDC scenarios. The framework includes a CDC synchronizer model implemented within the HDL partially compatible DEVS environment, enabling precise analysis of metastability violations based on setup time and hold time requirements. Circuit designers or related engineers can potentially solve timing issues such as CDC by incorporating DEVS-based analysis tools into the design pipeline.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call