Abstract
This paper demonstrates that another class of three-dimensional integrated circuits (3-D-ICs) exists, distinct from through-silicon-via-centric and monolithic 3-D-ICs. Furthermore, it is possible to create devices that are 3-D “at the device level” (i.e., with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of two-dimensional planar device architecture enables a wide range of interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.
Highlights
Bruce BurckelD. Bruce Burckel, “Device-level and module-level three-dimensional integrated circuits created using oblique processing,” J
Moore’s law,[1] an observation that the cost per transistor decreases as transistor density increases, following a roughly two year doubling period, has dominated the landscape of semiconductor research since it was first proposed in 1965
Such massive departures from silicon based, charge control, CMOS fabricated with optical lithography represent a long horizon endeavor, with many years of research
Summary
D. Bruce Burckel, “Device-level and module-level three-dimensional integrated circuits created using oblique processing,” J. Downloaded From: https://www.spiedigitallibrary.org/journals/Journal-of-Micro/Nanolithography,-MEMS,-and-MOEMS on 02 Nov 2021 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use. D. Bruce Burckel* Sandia National Laboratories, P.O. Box 5800, Albuquerque, New Mexico 87106, United States
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